Power Radio Station

Power Radio Station

Rapid.Space is manufacturing an open source small cell hardware (2x 1W, 2T2R) called the "Open Radio Station". See:

Rapid.Space is now looking for a partner to design or co-design a new radio system plat that can be produced in China and also abroad (Europe, Thailand, USA, etc.). The code name for this new product is "PRS" for "Power Radio Station".

Specs

Target specs are the following:

  PRS (short term) PRS (mid term) ORS (for reference)
Type 2T2R
4T4R
2T2R
4T4R
2T2R + 2T2R (two-band)
2T2R + 4T4R (two-band)
2T2R + 4T4R + 4T4R (three-band)
2T2R
4T4R
2T2R + 2T2R (two-band)
Output Power 40W to 80W per channel 40W to 80W per channel 1W per channel
10W per channel
Fronthaul interface CPRI (preferred)
or
eCPRI (subset)
or
RDMA (preferred)
or
PCIe
RDMA
or
PCIe
PCIe
Fronthaul interface speed 10 Gbps or less (CPRI)
or
25 Gbps or less (Ethernet)
25 Gbps (preferred)
100 Gbps
PCIe v4 up to 4 lanes
PCIe v3 with 1 lane
Split Split 8 Split 8 Split 8
Compression Optional (provided by us) Yes (provided by us) Optional (provided by us)
m-plane O-RAN yang models (preferred)
or
Anything else
O-RAN yang models (preferred)
or
Anything else
Register access over PCIe
Embedded OS Linux (with root access)
or
nothing
Linux (with root access) nothing
FPGA development environment any LiteX LiteX
FPGA SDK license any open source if possible proprietary (vivado)
FPGA origin any China if possible USA
Transceiver origin any China if possible USA or China
Synchronisation GPS (option) GPS
PTP
PTM (option)
GPS
PPS
PTM (PTP over PCIe)
Ability to include x86 or ARM SBC inside casing  if possible Yes Yes
Technical support Documentation and human Documentation and human (optional) Documentation and human (optional)

Quality

We need complete test coverage.

  PRS (short term) PRS (mid term) ORS (for reference)
Signal quality test report (3GPP or other) Yes Yes Yes
M-plane unit test Yes Yes Yes
End-to-end test optional optional Yes

Licensing

We need to be able to manufacture the hardware anywhere and to modify the source code by ourselves in front of our customers, including in front of local governments. In order to achieve that, some form technology licensing is required, either directly with Rapid.Space or by setting independent companies jointly in various countries (ex. EU).

We prefer open source licensing but this is not required. We are OK for pay for software license either per unit, flat fee or a combination.

  PRS (short term) PRS (mid term) ORS (for reference)
Access to BOM and CAD files if possible Yes Yes
Hardware license any any open source
Access for firmware OS source code Yes Yes Yes
firmware OS license open source if possible open source N/A
Access for FPGA bitstream source code if possible Yes Yes
FPGA bitstream license any open source not open source
       
       

 

Integration Test Procedure

Rapid.Space can provide onsite integration test. 

Requirements:

  • BBU with CPRI [Rapid.Space]
  • Core Network [Rapid.Space]
  • RU in CPRI interface [RU vendor]
  • CPRI Line Rate less than 10Gbps (CPRI Line Rate less than Rate 7) [RU vendor]
  • Coaxial cables and antenuators [RU vendor]
  • UE or UE simulator [RU vendor]
  • RU CPRI interface documentations, including delay parameter (see below) [RU Vendor]

 

Preparation:

Connect SPF/fiber cable (SPF/fiber module) on 2 SPF ports of CPRI card in Rapid.Space BBU. Launch LTEENB with cpri config to confirm HW&SW lock, making sure BBU, CPRI, SFP module and cables work. 

 

Procedure:

SYNC Plane

Goal: CPRI HW&SW lock

Configure frequency (dl_earfcn), bandwidth (N_RB_DL), antennas(N_ANTENNA_DL, N_ANTENNA_UL), CPRI line rate (cpri_mult) and launch it to confirm HW and SW lock


User Plane

Goal: UE attached

Configure delay parameter (cpri_rx_delay,cpri_tx_delay)

  • cpri_rx_delay = T2a + Ta3 - Toffset
  • cpri_tx_delay = T12 + T2a

Here is an example from Lopcomm's RU: https://handbook.rapid.space/user/rapidspace-Lopcomm.RRH.Delay.Management.CPRI.Delay 

Try to attach UE.

 

 

 

4TR-20MHz-B7 enb.cfg reference:
 

#define TDD 0#define N_RB_DL 100#define N_ANTENNA_DL 4#define N_ANTENNA_UL 4{ //log_options: "all.level=error,all.max_size=0,nas.level=debug,nas.max_size=1,s1ap.level=debug,s1ap.max_size=1,x2ap.level=debug,x2ap.max_size=1,rrc.level=debug,rrc.max_size=1,phy.level=info,file.rotate=1G,file.path=/dev/null",// log_options: "all.level=warn,phy.level=debug,phy.max_size=1,rrc.level=debug,rrc.max_size=1", log_options: "all.level=error,rrc.max_size=1", log_filename: "/tmp/enb0.log", rf_driver: { name: "sdr", args: "dev0=/dev/sdr0@0", cpri_mapping: "hw", cpri_mult: "16", cpri_rx_delay: "25.47", cpri_tx_delay: "14.71", cpri_tx_dbm: "54", cpri_debug: 2, ifname: "cpri0", }, tx_gain: 0, rx_gain: 0, com_addr: "127.0.1.2:9001", mme_list: [ { mme_addr: "192.168.9.100", }, ], gtp_addr: "192.168.9.7", enb_id: 0x1A2D0, cell_list: [{ rf_port: 0, cell_id: 0x00, tac: 0x0001, n_id_cell: 0, root_sequence_index: 204, dl_earfcn: 3100, scell_list: [ ], } ], cell_default: { plmn_list: [{ plmn: "00101", reserved: false, attach_without_pdn: false, } ], n_antenna_dl: N_ANTENNA_DL, n_antenna_ul: N_ANTENNA_UL,#if TDD == 1 uldl_config: 2, sp_config: 7,#endif n_rb_dl: N_RB_DL, cyclic_prefix: "normal", phich_duration: "normal", phich_resource: "1", si_value_tag: 0, cell_barred: false, intra_freq_reselection: true, q_rx_lev_min: -70, p_max: 17, si_window_length: 40, sib_sched_list: [ { filename: "sib2_3.asn", si_periodicity: 16, }, ],#if N_RB_DL == 6 si_coderate: 0.30,#else si_coderate: 0.20,#endif si_pdcch_format: 2, n_symb_cch: 0, pdsch_dedicated: {#if N_ANTENNA_DL == 4 p_a: -6,#elif N_ANTENNA_DL == 2 p_a: -3,#else p_a: 0,#endif p_b: -1, },#if N_RB_DL == 6 pdcch_format: 1,#else pdcch_format: 2,#endif#if N_RB_DL == 6 prach_config_index: 15,#else prach_config_index: 4,#endif prach_freq_offset: -1, pucch_dedicated: { n1_pucch_sr_count: 11, cqi_pucch_n_rb: 1,#if TDD == 1 tdd_ack_nack_feedback_mode: "multiplexing", /* TDD only */#endif }, pusch_dedicated: { beta_offset_ack_index: 9, beta_offset_ri_index: 6, beta_offset_cqi_index: 6, }, pusch_hopping_offset: -1, pusch_msg3_mcs: 0,#if N_RB_DL == 6 initial_cqi: 5,#else initial_cqi: 3,#endif dl_256qam: true, ul_64qam: true, sr_period: 20, cqi_period: 40,#if N_ANTENNA_DL >= 2 m_ri: 8, transmission_mode: 3,#endif srs_dedicated: {#if N_RB_DL == 6 srs_bandwidth_config: 7, srs_bandwidth: 1,#elif N_RB_DL == 15 srs_bandwidth_config: 6, srs_bandwidth: 1,#elif N_RB_DL == 25 srs_bandwidth_config: 3, srs_bandwidth: 1,#elif N_RB_DL == 50 srs_bandwidth_config: 2, srs_bandwidth: 2,#elif N_RB_DL == 75 srs_bandwidth_config: 2, srs_bandwidth: 2,#else srs_bandwidth_config: 2, srs_bandwidth: 3,#endif srs_subframe_config: 3, srs_period: 40, srs_hopping_bandwidth: 0, }, mac_config: { ul_max_harq_tx: 28, dl_max_harq_tx: 28, }, pusch_max_its: 6, dpc: false, dpc_pusch_snr_target: 25, dpc_pucch_snr_target: 20, cipher_algo_pref: [], integ_algo_pref: [2, 1], inactivity_timer: 10000, srb_config: [ { id: 1, maxRetxThreshold: 32, t_Reordering: 45, t_PollRetransmit: 60, }, { id: 2 , maxRetxThreshold: 32, t_Reordering: 45, t_PollRetransmit: 60, } ], drb_config: "drb.cfg", meas_config_desc: { a1_report_type: "rsrp", a1_rsrp: -70, a1_hysteresis: 0, a1_time_to_trigger: 640, a2_report_type: "rsrp", a2_rsrp: -80, a2_hysteresis: 0, a2_time_to_trigger: 640, a3_report_type: "rsrp", a3_offset: 6, a3_hysteresis: 0, a3_time_to_trigger: 480, }, meas_gap_config: "gp0", ho_from_meas: true, },}

Thank You

  • Nexedi SA
  • 147 Rue du Ballon
  • 59110 La Madeleine
  • France
  • +33629024425

For more information, please contact Jean-Paul, CEO of Nexedi (+33 629 02 44 25).